/* linux/include/asm-arm/arch-at91sam9260/at91sam9260_smc.h
 * 
 * Hardware definition for the smc peripheral in the ATMEL at91sam9260 processor
 * 
 * Generated  12/07/2006 (15:04:00) AT91 SW Application Group from HSMC3_6105A V1.4
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9260_SMC_H
#define __AT91SAM9260_SMC_H

/* -------------------------------------------------------- */
/* SMC ID definitions for  AT91SAM9260           */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* SMC Base Address definitions for  AT91SAM9260   */
/* -------------------------------------------------------- */
#define AT91C_BASE_SMC       	0xFFFFEC00 /**< SMC base address */

/* -------------------------------------------------------- */
/* PIO definition for SMC hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PC6_CFCE1    	(1 << 6) /**< Compact Flash Enable 1 */
#define AT91C_PC7_CFCE2    	(1 << 7) /**< Compact Flash Enable 2 */
#define AT91C_PC11_NCS2     	(1 << 11) /**< Chip Select Line 2 */
#define AT91C_PC14_NCS3_NANDCS 	(1 << 14) /**< Chip Select Line 3 */
#define AT91C_PC8_NCS4_CFCS0 	(1 << 8) /**< Chip Select Line 4 */
#define AT91C_PC9_NCS5_CFCS1 	(1 << 9) /**< Chip Select Line 5 */
#define AT91C_PC13_NCS6     	(1 << 13) /**< Chip Select Line 6 */
#define AT91C_PC12_NCS7     	(1 << 12) /**< Chip Select Line 7 */


/* -------------------------------------------------------- */
/* Register offset definition for SMC hardware peripheral */
/* -------------------------------------------------------- */
#define SMC_SETUP0 	(0x0000) 	/**<  Setup Register for CS 0 */
#define SMC_PULSE0 	(0x0004) 	/**<  Pulse Register for CS 0 */
#define SMC_CYCLE0 	(0x0008) 	/**<  Cycle Register for CS 0 */
#define SMC_CTRL0 	(0x000C) 	/**<  Control Register for CS 0 */
#define SMC_SETUP1 	(0x0010) 	/**<  Setup Register for CS 1 */
#define SMC_PULSE1 	(0x0014) 	/**<  Pulse Register for CS 1 */
#define SMC_CYCLE1 	(0x0018) 	/**<  Cycle Register for CS 1 */
#define SMC_CTRL1 	(0x001C) 	/**<  Control Register for CS 1 */
#define SMC_SETUP2 	(0x0020) 	/**<  Setup Register for CS 2 */
#define SMC_PULSE2 	(0x0024) 	/**<  Pulse Register for CS 2 */
#define SMC_CYCLE2 	(0x0028) 	/**<  Cycle Register for CS 2 */
#define SMC_CTRL2 	(0x002C) 	/**<  Control Register for CS 2 */
#define SMC_SETUP3 	(0x0030) 	/**<  Setup Register for CS 3 */
#define SMC_PULSE3 	(0x0034) 	/**<  Pulse Register for CS 3 */
#define SMC_CYCLE3 	(0x0038) 	/**<  Cycle Register for CS 3 */
#define SMC_CTRL3 	(0x003C) 	/**<  Control Register for CS 3 */
#define SMC_SETUP4 	(0x0040) 	/**<  Setup Register for CS 4 */
#define SMC_PULSE4 	(0x0044) 	/**<  Pulse Register for CS 4 */
#define SMC_CYCLE4 	(0x0048) 	/**<  Cycle Register for CS 4 */
#define SMC_CTRL4 	(0x004C) 	/**<  Control Register for CS 4 */
#define SMC_SETUP5 	(0x0050) 	/**<  Setup Register for CS 5 */
#define SMC_PULSE5 	(0x0054) 	/**<  Pulse Register for CS 5 */
#define SMC_CYCLE5 	(0x0058) 	/**<  Cycle Register for CS 5 */
#define SMC_CTRL5 	(0x005C) 	/**<  Control Register for CS 5 */
#define SMC_SETUP6 	(0x0060) 	/**<  Setup Register for CS 6 */
#define SMC_PULSE6 	(0x0064) 	/**<  Pulse Register for CS 6 */
#define SMC_CYCLE6 	(0x0068) 	/**<  Cycle Register for CS 6 */
#define SMC_CTRL6 	(0x006C) 	/**<  Control Register for CS 6 */
#define SMC_SETUP7 	(0x0070) 	/**<  Setup Register for CS 7 */
#define SMC_PULSE7 	(0x0074) 	/**<  Pulse Register for CS 7 */
#define SMC_CYCLE7 	(0x0078) 	/**<  Cycle Register for CS 7 */
#define SMC_CTRL7 	(0x007C) 	/**<  Control Register for CS 7 */

/* -------------------------------------------------------- */
/* Bitfields definition for SMC hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP    (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR  (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP    (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE    (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR  (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE    (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD  (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE    (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE    (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE   (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM      (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  5) /**< (SMC) External NWAIT disabled. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT         (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW         (0x3 << 12) /**< (SMC) Data Bus Width */
#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) /**< (SMC) 8 bits. */
#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) /**< (SMC) 16 bits. */
#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF         (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN       (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN        (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS          (0x3 << 28) /**< (SMC) Page Size */
#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) /**< (SMC) 4 bytes. */
#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) /**< (SMC) 8 bytes. */
#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) /**< (SMC) 16 bytes. */
#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP    (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR  (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP    (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE    (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR  (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE    (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD  (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE    (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE    (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE   (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM      (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  5) /**< (SMC) External NWAIT disabled. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT         (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW         (0x3 << 12) /**< (SMC) Data Bus Width */
#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) /**< (SMC) 8 bits. */
#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) /**< (SMC) 16 bits. */
#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF         (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN       (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN        (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS          (0x3 << 28) /**< (SMC) Page Size */
#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) /**< (SMC) 4 bytes. */
#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) /**< (SMC) 8 bytes. */
#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) /**< (SMC) 16 bytes. */
#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP    (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR  (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP    (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE    (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR  (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE    (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD  (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE    (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE    (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE   (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM      (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  5) /**< (SMC) External NWAIT disabled. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT         (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW         (0x3 << 12) /**< (SMC) Data Bus Width */
#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) /**< (SMC) 8 bits. */
#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) /**< (SMC) 16 bits. */
#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF         (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN       (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN        (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS          (0x3 << 28) /**< (SMC) Page Size */
#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) /**< (SMC) 4 bytes. */
#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) /**< (SMC) 8 bytes. */
#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) /**< (SMC) 16 bytes. */
#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP    (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR  (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP    (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE    (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR  (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE    (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD  (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE    (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE    (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE   (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM      (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  5) /**< (SMC) External NWAIT disabled. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT         (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW         (0x3 << 12) /**< (SMC) Data Bus Width */
#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) /**< (SMC) 8 bits. */
#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) /**< (SMC) 16 bits. */
#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF         (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN       (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN        (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS          (0x3 << 28) /**< (SMC) Page Size */
#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) /**< (SMC) 4 bytes. */
#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) /**< (SMC) 8 bytes. */
#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) /**< (SMC) 16 bytes. */
#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP    (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR  (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP    (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE    (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR  (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE    (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD  (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE    (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE    (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE   (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM      (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  5) /**< (SMC) External NWAIT disabled. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT         (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW         (0x3 << 12) /**< (SMC) Data Bus Width */
#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) /**< (SMC) 8 bits. */
#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) /**< (SMC) 16 bits. */
#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF         (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN       (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN        (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS          (0x3 << 28) /**< (SMC) Page Size */
#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) /**< (SMC) 4 bytes. */
#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) /**< (SMC) 8 bytes. */
#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) /**< (SMC) 16 bytes. */
#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP    (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR  (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP    (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE    (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR  (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE    (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD  (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE    (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE    (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE   (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM      (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  5) /**< (SMC) External NWAIT disabled. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT         (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW         (0x3 << 12) /**< (SMC) Data Bus Width */
#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) /**< (SMC) 8 bits. */
#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) /**< (SMC) 16 bits. */
#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF         (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN       (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN        (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS          (0x3 << 28) /**< (SMC) Page Size */
#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) /**< (SMC) 4 bytes. */
#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) /**< (SMC) 8 bytes. */
#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) /**< (SMC) 16 bytes. */
#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP    (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR  (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP    (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE    (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR  (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE    (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD  (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE    (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE    (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE   (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM      (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  5) /**< (SMC) External NWAIT disabled. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT         (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW         (0x3 << 12) /**< (SMC) Data Bus Width */
#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) /**< (SMC) 8 bits. */
#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) /**< (SMC) 16 bits. */
#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF         (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN       (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN        (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS          (0x3 << 28) /**< (SMC) Page Size */
#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) /**< (SMC) 4 bytes. */
#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) /**< (SMC) 8 bytes. */
#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) /**< (SMC) 16 bytes. */
#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP    (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR  (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP    (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE    (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR  (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE    (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD  (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE    (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE    (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE   (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM      (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  5) /**< (SMC) External NWAIT disabled. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT         (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW         (0x3 << 12) /**< (SMC) Data Bus Width */
#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) /**< (SMC) 8 bits. */
#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) /**< (SMC) 16 bits. */
#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF         (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN       (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN        (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS          (0x3 << 28) /**< (SMC) Page Size */
#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) /**< (SMC) 4 bytes. */
#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) /**< (SMC) 8 bytes. */
#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) /**< (SMC) 16 bytes. */
#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */

#endif /* __AT91SAM9260_SMC_H */
